Senior ASIC Design Engineer RTL/Timing ExpertHewlett Packard Enterprise Development LP • United States

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Senior ASIC Design Engineer RTL/Timing Expert

Hewlett Packard Enterprise Development LP

United States

United States

Jetzt Bewerben

Über

A leading technology company in Sunnyvale, California, seeks an experienced engineer to join the Physical design team. The role involves optimizing floorplan and timing closure while validating designs with the Verification team. Candidates must have a Bachelor's degree in Electrical Engineering and over 10 years of experience, alongside strong analytical skills and proficiency in Verilog/System Verilog. This position promotes a collaborative environment focused on innovation and growth. #J-18808-Ljbffr

United States

Sprachkenntnisse

English

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