Über
At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we're looking for innovators who are as committed to shaping the future of cybersecurity as we are. We believe collaboration thrives in person. That's why most of our teams work from the office full time, with flexibility when it's needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes. Job Description
Join our Asic team and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design engineers to hit aggressive performance, power, and schedule goals. Your impact: Write clear design and micro-architecture specifications. Design Systemverilog Rtl that meets area, performance, and power targets. Verify your blocks with simulation, emulation, formal methods, and silicon bring-up. Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features. Partner with physical-design teams: review synthesis/timing reports, rewrite rtl to close critical paths, and consult on floor-planning for congestion/routability. Innovate: pilot ai-driven design or verification flows that cut schedule risk. Qualifications
Your experience: Bs in ee, ce, or cs (msee or equivalent military experience preferred). 10+ years' front-end asic design ownership, shipping 2+ chips to mass production. Solid experience with pcie core integration and lab validation. Expert systemverilog rtl skills. Scripting proficiency (python, c/c++, perl, bash or tcsh). Demonstrated strength in: Defining micro-architecture from high-level requirements. Datapath design expertise for intricate synch/asynch digital logic. Debugging across simulation, emulation, and silicon. Analyzing timing, power, and area reports and driving fixes. Excellent leadership, collaboration, and written/verbal communication. Preferred / nice-to-have: Networking or cybersecurity domain knowledge. Experience with ddr5 memory, ethernet (ieee 802.3), or search-algorithm accelerators. Formal-verification ownership. Hands-on silicon validation and lab bring-up.
Sprachkenntnisse
- English
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