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We are seeking an experienced Full Chip Lead to own end-to-end physical implementation and timing closure of a complex 28nm FDSOI full chip. The role requires deep hands-on expertise in large-scale static timing constraints (SDCs), multi-mode multi-corner (MMMC) flows, and cross-functional coordination from RTL handoff through signoff and tape-out. Full-Chip Ownership
Own full-chip integration, physical implementation, and signoff for a 28nm FDSOI SoC from netlist freeze to GDS. Drive floorplanning, power planning, clocking architecture, and chip assembly across multiple subsystems and IPs. Act as the technical owner for full-chip quality, risk management, and delivery. Timing Constraints & SDC Leadership (Critical)
Own and maintain large, complex SDC environments including: multiple clock domains (PLL, Client, async, low-power clocks), generated clocks, clock grouping, false paths, multicycle paths, IO constraints, DFT constraints, and mode-specific constraints. Lead SDC strategy, development, validation, and cleanup across block and top levels. Ensure SDC consistency and correctness across RTL, synthesis, P&R, STA, and signoff tools. Debug and resolve constraint-related timing issues, over-constraining/under-constraining risks, and tool mismatches. Timing Closure & STA
Drive MMMC timing closure across all functional, test, LP, and voltage modes. Hands-on ownership of setup/hold, clock reconvergence pessimism (CRPR), SI-aware timing, and OCV/AOCV/POCV. Lead pre- and post-route STA, ECO strategy, and late-stage closure. Coordinate timing signoff with foundry, IP vendors, and customers. Low Power & FDSOI-Specific Aspects
Drive power intent implementation (UPF/CPF), including multi-Vt, power domains, isolation, level shifters, retention. Leverage FDSOI body biasing (BB) techniques for PPA optimization. Collaborate closely with power and architecture teams to meet aggressive power targets. DFT, IO, and Signoff Collaboration
Coordinate with DFT teams on scan, at-speed test modes, test clocks, and test-specific SDCs. Work closely with packaging/IO teams for pad constraints and SI awareness; signoff teams for DRC/LVS, EM/IR, noise, and reliability. Technical Leadership
Mentor block-level leads on SDC best practices, timing closure strategy, and ECO flows. Drive flow standardization, checklists, and automation scripts (Tcl/Perl/Python). Provide clear status, risk assessment, and mitigation plans to program management and stakeholders. Required Technical Skills Must-Have
12+ years of experience in ASIC Physical Design/Full Chip Integration. Proven experience as Full Chip Lead on advanced nodes (≤28nm preferred). Deep expertise in SDC authoring, review, and debugging at scale. Strong hands-on experience with PrimeTime/PrimeTime SI, ICC2/Innovus, MMMC flows, and signoff methodology. Solid understanding of clocking architectures, CDC concepts, and async design; hold closure, ECO strategies, and late-stage timing fixes. FDSOI / Low Power (Highly Preferred)
Direct experience with 28nm FDSOI. Knowledge of body-biasing, low-Vdd operation, and leakage optimization. Strong UPF/CPF understanding in complex SoCs. Scripting & Automation
Strong Tcl scripting (mandatory). Perl/Python for flow automation and analysis (preferred). Soft Skills & Leadership
Ability to act as single-threaded owner for full-chip timing and P&R. Strong cross-team communication with RTL, DFT, signoff, and program teams. Comfortable in customer-facing technical discussions and escalations. Calm under schedule pressure; structured problem solver. Diverse Lynx LLC is an Equal Employment Opportunity employer. All qualified applicants will receive due consideration for employment without any discrimination. All applicants will be evaluated solely on the basis of their ability, competence, and their proven capability to perform the functions outlined in the corresponding role. We promote and support a diverse workforce across all levels in the company.
Sprachkenntnisse
- English
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