RISC-V CPU Architect/RTL Lead
JDWK
- Austin, Texas, United States
- Austin, Texas, United States
Über
Lead the selection, development, and integration of RISC-V CPU cores Description
About Us
We are a small, fast-moving team building RISC-V–based SoCs and developing automation tools that make custom silicon design more accessible. Our mission is to combine deep hardware design expertise with modern software-driven methodologies. We’re looking for a
CPU RTL Lead
to take ownership of our RISC-V core development — someone who understands the landscape of open-source CPU designs, knows their strengths and weaknesses, and can architect and implement a world-class custom core optimized for our application and toolchain goals. Role Overview
As the
CPU RTL Lead , you’ll drive the design and implementation of a RISC-V processor core — from high-level architecture through synthesizable RTL. You will evaluate existing open-source cores, define architectural tradeoffs, and implement new features or custom extensions as needed. You’ll also establish and oversee verification, synthesis, and performance analysis flows for the CPU subsystem. This role combines
hands-on RTL design ,
microarchitecture definition , and
technical leadership
in a startup setting where your work will directly shape our silicon roadmap. Key Responsibilities
Own the RISC-V CPU microarchitecture and RTL implementation , including pipeline, ISA extensions, and interfaces. Evaluate and compare open-source RISC-V cores
(e.g., Rocket, BOOM, CVA6, Ibex, etc.), assessing performance, scalability, and design quality. Architect enhancements or new cores
tailored to specific application domains and system-level requirements. Develop and maintain high-quality, synthesizable RTL
in SystemVerilog or Verilog. Define verification strategy
and collaborate on UVM, formal, or FPGA-based validation of the core. Optimize for PPA
(Performance, Power, Area) targets through microarchitectural tuning and synthesis feedback. Collaborate closely with SoC, memory, and firmware teams
to ensure seamless CPU subsystem integration. Establish and maintain coding standards, linting, and continuous integration flows
for RTL and verification. Mentor engineers
and help build a small but high-performing front-end design team. Requirements
7+ years of RTL design experience , including at least one CPU or DSP core development project from concept to silicon. Deep understanding of CPU microarchitecture , including pipelines, branch prediction, hazards, caches, MMUs, and clock/power domains. Strong knowledge of the RISC-V ISA , privilege architecture, and optional extensions. Hands-on experience with at least one open-source RISC-V core , such as Rocket, CVA6 (Ariane), Ibex, or BOOM. Ability to analyze and improve open-source designs , recognizing their architectural and verification tradeoffs. Proficiency in SystemVerilog/Verilog RTL design , simulation, and synthesis. Experience with EDA tools
(Synopsys, Cadence, or open-source flows) for synthesis and linting. Solid understanding of verification methodologies
(UVM, formal verification, or constrained-random testing). Strong communication and cross-functional collaboration skills . Comfort working in a startup environment —hands-on, self-directed, and resourceful. Preferred Qualifications
Familiarity with
Chisel, SpinalHDL, or TL-Verilog . Experience with
performance modeling
or cycle-accurate simulation frameworks. Background in
FPGA prototyping
or hardware/software co-simulation. Contributions to
open-source RISC-V or hardware projects . Experience leading or mentoring small design teams. What We Offer
The opportunity to
lead CPU architecture
for next-generation RISC-V SoCs. A
high-impact role
with deep technical ownership and creative freedom. Collaborative culture with strong engineering focus and minimal bureaucracy. Flexible work arrangements and competitive compensation and benefits.
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Sprachkenntnisse
- English
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