Über
Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog Translate architectural specifications into clean, efficient, and scalable microarchitectures Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
Required Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in RTL design Strong hands-on experience with Verilog/SystemVerilog Solid understanding of synchronous digital design and microarchitecture principles Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
Sprachkenntnisse
- English
Hinweis für Nutzer
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