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Über
10+ years Key Responsibilities Design and implement
RTL for complex ASIC/SoC subsystems
using
SystemVerilog/Verilog . Architect and implement
high-performance interconnect fabrics
including
NoC, AXI/AHB/APB bus systems , and memory subsystems. Work with architecture teams to translate
micro-architecture specifications into synthesizable RTL . Optimize designs for
performance, power, and area (PPA) . Support
functional verification
through testbench collaboration, debug, and coverage closure. Collaborate with
physical design teams
to ensure timing closure, clocking strategy, and floorplan alignment. Participate in
design reviews, code reviews, and architecture discussions . Support
post-silicon debug and bring-up
when required. Required Qualifications 10+ years of ASIC front-end design experience . Strong expertise in
RTL design using Verilog/SystemVerilog . Proven experience designing
SoC subsystems and interconnect architectures . Deep understanding of
AMBA protocols (AXI, AHB, APB) . Experience implementing
Network-on-Chip (NoC) or scalable bus fabrics . Solid understanding of
pipelining, arbitration, coherency, memory ordering, and high-throughput datapaths . Familiarity with
synthesis, timing analysis, and low-power design techniques . Experience working with
EDA tools such as Synopsys, Cadence, or Siemens flows . Strong debugging and problem-solving skills. Preferred Qualifications Knowledge of
high-bandwidth memory systems (HBM, DDR) . Experience designing
high-performance compute engines in GPU or NPU is a plus . Familiarity with
chiplet architectures or advanced packaging . Experience with
performance modeling and architecture exploration . Scripting experience in
Python, Perl, or Tcl . Education BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field .
Sprachkenntnisse
- English
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