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Über
UPF/VCLP with Low Power expertise Location: Bay area (onsite) Duration : 12+ Months Job Description : UPF/VCLP with Low Power expertise ng a skilled
Low Power Design & Verification Engineer
with strong expertise in
UPF (Unified Power Format)
and
VCLP (VC Low Power) . The ideal candidate will be responsible for defining, implementing, and verifying low-power architectures in complex SoC designs, ensuring compliance with power intent and design specifications. Key Responsibilities Develop and implement
power intent using UPF (IEEE 1801) Define and manage
power domains, power states, and supply networks Perform
low power verification using VCLP (Synopsys VC LP) Thanks Shaik Sadeq Email: Sadeq@infobahnsw.com
Sprachkenntnisse
- English
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