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Über
Job Description Renesas is a key supplier to the world's leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi‑billion dollar, a publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multicultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast‑growing data‑economy related markets such as infrastructure and data centers and strengthening our presence in the industrial/IoT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what's next in electronics.
This is a Senior Manager position for a qualified individual to work in Renesas' Analog and Connectivity Business Group. The primary role is to manage a digital design team and lead the team to develop IC products. The candidate will work together with the team in the other sites of the United States and the team in China and contribute to all aspects of development from product conception to production release. The candidate should have experience in leading design teams in VLSI IC development, with a proven track record of delivering high‑quality silicon on time and within cost targets. The candidate will also be responsible for design documentation, silicon evaluation, circuit debugging, production test development support, and customer and applications support. He/she will also be involved in the specification of technology requirements for future products.
Qualifications
Education: MSEE or PH.D. in Electrical Engineering with 8+ years of relevant industry experience.
Experience as a people manager or team lead position, people management skills
Proven experience in SOC architecture, AHB/APB/AXI, bus matrix and interface protocols – USB, I2C/I3C, SPI, UART; packet‑oriented protocols.
Good knowledge of embedded memories – SRAM, OTP, MTP and EE/Flash memory
Good knowledge of design flow. Hands on in chip architecture definition, partition, assignment, RTL coding, simulation, synthesis, DFT and timing check
Strong communication and teamwork skills
Highly motivated and creative individuals preferred
Bilingual and Mandarin fluency would be a plus
DDR DRAM and Flash memory knowledge would be a plus
Mixed signal knowledge and chip experience is highly preferred.
Additional Information The expected annual pay range for this position is $190K- $240K. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.
Renesas offers a full range of elective benefits including medical, health savings account (with applicable medical plan), dental, vision, health and/or dependent care flexible spending accounts, pre‑tax commuter benefits, life insurance, AD&D, and pet insurance. In addition to elective benefit options, benefited employees receive company‑paid life insurance and AD&D, LTD, short term medical benefits as well as paid sick time, paid holidays, and accrued paid vacation. New employees will attend a detailed benefit orientation to learn more about our many benefits and resources.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement (https://jobs.renesas.com/diversity-and-inclusion).
We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in‑office days are Tuesday through Thursday for innovation, collaboration and continuous learning.
Department
Engineering
Location
San Jose
Remote
No
#J-18808-Ljbffr
Sprachkenntnisse
- English
Hinweis für Nutzer
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