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US, Arizona, Phoenix:
US, California, Folsom:
US, Texas, Austintime type:
Full timeposted on:
Posted Todaytime left to apply:
End Date: April 14, 2026 (3 days left to apply)job requisition id:
JR0282903# **Job Details:**## Job Description:The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.**Responsibilities:*** Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.* Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.* Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.* Analyzes results and makes recommendations to fix violations for current and future product architecture.* Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.* Optimizes design to improve product level parameters such as power, frequency, and area.* Participates in the development and improvement of physical design methodologies and flow automation.## **Qualifications:**You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. **Minimum Qualifications:*** Master's Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field with 6+ years of experience -OR- Bachelor's Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field with 9+ years of experience.* 6+ years experience with APR tools, either Synopsys or Cadence.* 6+ years experience with static timing analysis (STA).* 6+ years experience with TCL, Python or Perl programming.**Preferred Qualifications:*** Experience in all aspects of physical design using Synopsys or Cadence tools.* Strong background with industry standard tools for synthesis, place and route, and tape out flows.* Technical expertise in physical design verification methods such as timing signoff, formal verification, and low power static signoff.* The ideal candidate will also have excellent communication, teamwork, and problem-solving skills.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, Arizona, Phoenix## Additional Locations:US, California, Folsom, US, Texas, Austin## Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change.\*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr
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