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UVM verification consultant for mixed-signal power controllers.
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Responsibilities
- Design and implement script-automated UVM testbench and IP creation framework.
- Developing architectures, methodologies and UVM testbenches for mixed signal ASIC verification.
- Advising on RTL and testbench architectures to maximise reuse and improve verification quality.
- Specifying and writing models, coverage goals and tests to reach verification targets.
- Scripting for and supporting use of design tools including SOS version control, DVT Eclipse and Cadence tools.
- Architecting, implementing and verifying on-die memory protection algorithms. xcfaprz
- Requirement tracing, verification planning and coverage analysis for signoff.
Contact:
#J-18808-Ljbffr
Sprachkenntnisse
- English
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