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Über
Location: Bay Area, CA
Duration: Full time
Job Overview:
We are looking for a highly skilled
Physical Design Engineer
to work at block level and/or top level for high performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the
backend VLSI design flow
including
floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification.
The role requires expertise in
EDA tools, physical verification methodologies, power optimization, and performance tuning.
Key Responsibilities:
Block-Level Physical Design:
Floorplanning & Partitioning
- Define
optimal floorplan
with power grid, macro placements, and congestion analysis. Strong scripting experience. Placement & Optimization
- Perform
standard cell placement, legalization, and optimization
to improve area, power and timing. legalization, and optimization to improve area, power, and Clock Tree Synthesis (CTS)
- Design and optimize
low-skew, high-performance clock networks. Routing & DRC Closure
- Ensure
successful global and detailed routing , meeting design rule constraints. Timing Closure
- Work on
setup/hold timing violations , signal integrity, and cross-talk reduction using
static timing analysis (STA). Power & IR Drop Analysis
- Optimize
power planning, power Integrity (IR drop, EM), and leakage reduction techniques. Top-Level Physical Design:
Chip-Level Floorplanning & Hierarchical Design
- Manage
top-level layout planning . pin assignments, and cross-block optimizations. Strong scripting experience. Clock & Power Distribution
- Design robust
clock trees and power delivery networks (PDN). Integration of IP & Sub-blocks
- Ensure seamless integration of IP blocks and handle complex routing challenges. Chip Assembly & Sign-Off
- Perform
final netlist-to-GDSII implementation , addressing physical and electrical verification. DFT Integration
- Work with
Design for Test (DFT) teams
to ensure scan chain connectivity and testability.
Sprachkenntnisse
- English
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