IP Design Verification

This Design Verification Intern role puts you at the heart of building the next generation of compute, not just watching from the sidelines. You'll help push high‑speed digital and mixed‑signal blocks to their limits, write and run simulations that uncover real bugs, and see your work show up in decisions that ship real hardware. You'll collaborate closely with experienced engineers, learn modern DV flows end‑to‑end, and leave with the kind of hands‑on impact most internships only talk about.

Please note this is a 12-16 month internship.

This role is hybrid based out of Toronto, Canada or Santa Clara, California office.

Who You Are

• Senior-year undergrad or grad student in EE, CE, CS, or a related field.
• Comfortable with Verilog, SystemVerilog, or scripting languages.
• Familiar with computer architecture and interested in how chips really work.
• Analytical, curious, and ready to dive into the details of performance and functionality.

What We Need

• Develop tests for functional and performance verification of chip inter-connection IP.
• Write and debug RTL, testbenches, and simulation environments.
• Support coverage, checkers, and verification infrastructure across subsystems.
• Help build tooling and workflows that scale across pre-silicon to post-silicon.

What You Will Learn

• Industry-proven verification flows including simulation, emulation, and coverage.
• The full DV lifecycle: test planning, debug, execution, and closure.
• Collaboration with design, architecture, and performance teams in a real-world chip project.
• How AI is playing a significant role in the development of code, tools and flows.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.