Design For Test Engineer
Advanced Micro Devices
- Cambridge, England, United Kingdom
- Cambridge, England, United Kingdom
Über
THE ROLE We are seeking an experienced Design For Test engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and experience in DFT methodologies, particularly in the context of CPU core design and development.
As a DFT engineer in AMD’s CPU Cores team, you will have an outstanding opportunity to work on AMD’s next‑generation CPU core designs. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.
As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first‑pass silicon success.
THE PERSON A successful candidate will exhibit strong knowledge in Design for Testability (DF elkaar) and possess solid experience, complemented by a robust, self‑motivated work ethic and strong leadership qualities.
The ideal candidate should demonstrate a genuine passion for modern, complex processor architectures, digital design and verification, and an overall enthusiasm for DFT. As a collaborative team player, you will have outstanding communication skills and experience in working effectively with engineers across various locations and time zones. Your strong analytical and problem‑solving abilities will empower you to tackle challenges enthusiastically and with a willingness to learn.
Additionally, you should have a keen eye for detail and the capability to think critically. The role requires a proactive self‑starter who can take initiative and independently drive tasks to successful completion.
KEY RESPONSIBILITIES
Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies into AMD products.
Define and implement DFT architecture mắt ng features for next generation multi‑core microprocessor designs and support their verification effort.
Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs.
Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration.
Work closely with DFT Tool Vendors and drive improvements based on the testability requirements.
Develop efficient DFx flows and methodology compatible with front end and back end design flows.
Work with the product, test engineering teams and post‑silicon debug teams to ensure successful silicon bring‑up, help root‑cause any silicon failures and enhance yield learning & improvement.
Mentor and coach junior engineers.
REFERRED EXPERIENCE
Strong experience in Scan based testing and industry standard ATPG CAD tools desired.
Knowledge of fault models including Stuck‑at, Transition, Gate‑Exhaustive, Path Delay, IDDQ, Cell Aware etc.
Knowledge of ATPG pattern verification and gate‑level simulation flows using Synopsys VCS and Verdi or other state‑of‑the‑art EDA tools.
Experience in MBIST implementation and verification will be a strong plus.
Good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), SSH, Test Compression, OCC etc.
Excellent Verilog RTL coding, scripting (using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills are critical.
Good understanding of STA concepts having handled DFT timing closure before would be a plus.
Experience in Spyglass based DFT DRC checks at RTL level would be a plus.
Experience with Synopsys Design Compiler / Test Compiler / Fusion Compiler etc would be a plus.
Prior experience in working with Version control systems like Perforce, Git etc would be critical.
Prior work experience in high‑performance and Floating? low‑power designs would be a huge bonus.
Understanding of low‑power design flows such as power/clock gating, multi‑Vt and voltage/frequency scaling etc will be a plus.
Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks would be a plus.
Familiarity with System Verilog and UVM would be a plus.
Exposure to post‑silicon testing and tester pattern debug are major assets.
Strong problem solving and debug skills across various levels of design hierarchies.
Musthorende good communication skills and the ability to work in a worldwide team environment.
Exposure to leadership or mentorship is an asset.
ACADEMIC CREDENTIALS
Bachelors or Masters or PhD in Computer Engineering / Electrical Engineering / Electronics Engineering.
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Benefits offered are described: AMD benefits at a glance.
AAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑basedointer recruitment services. AMD and its subsidiariesropath are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political andlahatادث أو three/bin third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.m
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy faced” is available here.
This posting is for an existing vacancy.
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Sprachkenntnisse
- English
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