Physical Design Engineer

Physical Design Engineer -
Location: San Jose OR Irvine, CA

Our client develops specialized semiconductor solutions for the edge, building processors capable of running AI workloads alongside bandwidth-intensive sensors and wireless platforms. Their systems are designed to interpret and analyze RF data in ways that were not previously possible.

They are seeking an experienced Senior SoC/ASIC Physical Design Engineer to take the lead on chip implementation efforts and guide the design through final closure. The role involves working closely with RTL and other cross-functional teams while shaping and improving the physical design flow. The engineer will develop and refine methodologies aimed at achieving strong PPA results and efficient execution. This position will play a key part in meeting aggressive closure and tapeout goals with an optimized team and resource structure.

RESPONSIBILITIES:

• Build and refine the PD flow: Develop a modern physical design environment using current EDA tool capabilities and ML-driven optimizations to improve PPA, streamline resources, and accelerate closure and tapeout schedules.
• Own full-chip PD execution: Handle block-level and top-level implementation—including synthesis, floor planning, power grid creation, place and route, timing analysis, noise analysis, physical verification, EM/IR checks, and signoff tasks.
• Enhance methodology and automation: Develop and maintain PD methodologies and the supporting scripts that improve efficiency from implementation through final signoff.
• Collaborate across teams: Partner closely with RTL, DFT, and ASIC design groups to validate architectural assumptions, define timing/power/area expectations, and evaluate design tradeoffs.
• Drive closure with measurable results: Apply a data-driven approach to identify and resolve timing, design, and flow challenges to ensure predictable milestone completion.
• Lead final signoff activities: Oversee all signoff requirements, including STA, noise analysis, LEC, physical verification, and power integrity analysis.

QUALIFICATIONS:

• BS in electrical engineering or equivalent. MS is preferred but not required.
• At least 10 years of experience working in ASIC/SoC physical design and developing PD flows.
• Strong background in RTL-to-GDSII implementation and final signoff, including:
• Hands-on experience with Synopsys tools and a solid understanding of their internal behavior.
• Expertise in synthesis, place and route, timing analysis, formal checks, CDC analysis, and power evaluation.
• Understanding of advanced CMOS and FinFET technologies, including leakage, dynamic power, and device characteristics.
• Familiarity with DFT methods—such as scan, MBIST, and LBIST—and how they impact the physical design process.
• Skilled in scripting and automation using Python, Tcl, Perl, and shell languages, as well as Makefile-based flow.
• Comfortable analyzing extraction data, tracking quality-of-results metrics, and working with power-management techniques such as DVFS, SVS, and multi-rail SRAM approaches.
• Proven ability to collaborate effectively across teams, take ownership of closure tasks, and solve issues proactively in fast-moving environments.

INCENTIVES & BENEFITS:

• Location: San Jose or Irvine, CA
• To $250K Base Salary
• Equity
• 401(k) w/ 3% Match
• Comprehensive medical, dental, vision, and life insurance
• PTO and paid holidays
• Relocation Assistance
• H1B Visa Sponsorship (Transfers only)