Director Digital Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at

Job Description  

We are looking for a Director Digital Design Engineer with experience developing microarchitecture and implementing front-end circuit design, including RTL, synthesis, IP integration, and block-level verification, for high-performance network controllers' connectivity solutions. The candidate must have a good knowledge of communication and interface standards and base protocols such PCIe, Ethernet and UALink (optional).  This position will be required on site.  

Basic Qualifications:  

• Strong academic and technical background in Electrical or Computer Engineering. A bachelor's EE is required, and a Master's degree is preferred.  
• 12+ years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.  
• 5+ years' experience in technical leadership or management experience.   
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare in advance for customer meetings, and work mostly independently with minimal guidance and supervision.  
• Entrepreneurial, open-minded, and with a can-do attitude. Think and act fast, always keeping the customer in mind  
• Authorized to work in the US and start immediately.  

Required Experience:  

• Hands-on, good knowledge of Ethernet or UALink 
• Proven front-end design expertise in architecture, RTL, simulations, synthesis, timing closure, GLS, DFT, etc.  
• Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production.     Extensive collaboration with software development teams is needed.   
• Experience using Cadence and/or Synopsys digital design tools/flows.   
• Knowledge in design for test (DFT), stuck at, and transition scan test insertion.  
• Familiarity with UVM-based design verification  
• Silicon bring-up and debug expertise  
• Small-geometry CMOS (≤ 28nm, 16nm) design  

Preferred Experience:   

• Scripting with Python or other equivalent programming languages.  
• Development/support for PCIe and DDR-based products. PCIe or Ethernet Switch products. Familiarity with security standards  
• Strong methodology mindset with a track record of developing ASIC development methodologies.  

Your base salary will be determined based on location, experience, and employees' pay in similar positions. The base salary range is $218,500 USD – $260,000 USD. This position can be hired as a Senior Manager Level or Director Level. 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.