SoC Design Verification Engineer San Diego, CA

Job Title: SoC Design Verification EngineerLocations: San Diego, CA or RemoteFull-Time: Salary + Benefits + BonusesResponsibilities:• Testbench development - System Verilog UVM and C tests• Integration/development of C tests/APIs and SW build flow• Integration/development of UVM mailboxes and HW/SW communication components• Integration of lower level UVM testbenches• Test plan development• Power Aware testbench development and simulations• Seamless porting between simulation/emulation/prototyping platforms• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto• Coverage collection and closure• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scopeMinimum Qualifications:• 5+ years of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HW/SW verification• Deep knowledge of System Verilog UVM and vertical testbench integration• Knowledge of low level HW/SW interaction and debug• Knowledge of multi CPU and debug architectures• Knowledge on AHB, AXI and APB Amba protocols• Experience with development of fully automated flowsPreferred Qualifications:• Experience with low level SW debug - disasm, Tarmac, trace• Experience with RISC-V and ARM CPU architectures• Experience with CoreSight architecture• Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security• Experience with coverage merging across simulation and emulation• Experience with Power Aware and Gate Level Netlist in Emulation• Experience with development of fully automated flows• Experience with Gate Level Simulations• Experience with Synopsys tools VCS & Verdi• Python Scripting #J-18808-Ljbffr