Principal/ Senior Principal Digital ASIC Circuit Design Engineer

The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions Business pushes the boundaries of innovation, redefines the leading edge of exotic new technologies, and drives advances in the sciences. One of our most challenging new fields is Transformational Computing, which combines the unique properties of superconductivity and quantum mechanics to develop radical new energy-efficient computing systems.

Our team is chartered with providing the skills to transform computing beyond Moore’s Law, advancing development of computer architectures, processing/memory subsystems, and large-scale high-performance computing systems. You’ll work in a fast-paced team environment alongside a broad array of scientists and engineers to make these processing solutions a reality and deliver remarkable new advantages to the warfighter.

We are seeking a front-end ASIC design engineer for design and verification of full-custom digital circuits. Must be proficient in Verilog, System Verilog or VHDL RTL coding, write functional test benches and have a thorough understanding of synchronous digital design concepts. Must be able to create a functional verification plan based on requirements of the circuit. Able to generate manufacturing test plans. Must be knowledgeable in synthesis, SDC constraints, formal verification, and static timing. Knowledge of scan insertion and ATPG is a plus. Able to interface with place and route engineers for floor planning and clock tree constraints and timing closure. Automated place and route and physical verification knowledge is a plus. Must have strong written and oral communication skills.

Responsibilities:

• Circuit behavioral coding in Verilog, System Verilog or VHDL RTL
• Circuit synthesis, formal verification, and static timing using state-of-the-art digital ASIC design tools
• Developing verification plans based on requirements of the circuit and creating circuit functional test benches in RTL
• Generating manufacturing test vectors and manufacturing circuit test plan
• Help develop automated procedures to streamline digital design procedures

This position requires 100% onsite work at our Advanced Technology Lab in Linthicum, MD.

Candidate must be a US Citizen and have the ability to obtain/ maintain a security clearance once on board.

This position can be filled at the Principal level OR the Sr. Principal level. Qualifications for both are listed below:

Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:

• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with STEM MS; 1 year with STEM Phd)
• Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
• Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
• Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium, Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus
• Candidate must be a US Citizen and have the ability to obtain/ maintain a security clearance once on board.

Preferred Qualifications:

• Advanced Degree - either MS or PhD
• Current security clearance or eligibility
• Experience with chip level integration and ASIC chip lead - Strong design automation skills
• Experience in CAD design network, tool configuration, and data management
• Familiarity with custom layout in Virtuoso, and physical verification (LVS/DRC) in Assura or Calibre Familiarity with revision control and EDA standard formats used in cell/library development and modeling – Liberty (timing model), SDC (Synopsys Design Constraints)

Basic Qualifications for Sr. Principal Digital ASIC Circuit Design Engineer Level:

• Bachelor's degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with STEM related MS, 4 years with STEM related PhD)
• Experience with full product life cycle (requirements, design, implementation, test) of ASIC design
• Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
• Proficiency with current ASIC design tools for all phases described below: Simulation – Mentor ModelSim, Cadence Excelium Incisive or Synopsys VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus

Preferred Qualifications:

• Advanced Degree - either MS or PhD
• Current security clearance
• Experience with chip level integration and ASIC chip lead - Strong design automation skills
• Experience in CAD design network, tool configuration, and data management