Senior Principal DFT Design Engineer

Cadence Design Systems

United States

United States

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Über

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.Requirements;US citizenship preferred.* Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)* Should possess intimate knowledge of DFT insertion flows* Basic scan chain insertion using synthesis or other software tools* Experience in compression scan insertion, LBIST and other scan technologies* Intimate knowledge of memory build-in self-test (MBIST)* Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals* Debug and Analysis of failures to improve fault coverage* Verification of ATPG testbenches and debugging root cause of simulation mis-compares* Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687* Knowledge of timing analysis and equivalency checks would be added bonus* Ability to work in collaborative team environment* Prior experience with Cadence tools and flows is highly desirable* Should be able to finish DFT tasks independently* Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems* Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers* Self-driven and committed individual who can work in a fast-paced project environment## **We’re doing work that matters. Help us solve what others can’t.****Equal Employment Opportunity Policy:**Cadence is committed to equal employment opportunity throughout all levels of the organization.We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com.**Privacy Policy:**Job Applicant If you are a job seeker creating a profile using our careers website, please see the .E-Verify Cadence participates in theE-Verify program in certain U.S. locations as required by law.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr

United States

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English

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