Senior Digital Design EngineerQuantum Flagship • Cambridge, England, United Kingdom

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Senior Digital Design Engineer

Quantum Flagship

Cambridge, England, United Kingdom

Cambridge, England, United Kingdom

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Über

Cambridge, UK | Full-time or Part-time | Permanent | Salary: £75,000 to £100,000 DOE We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter. About us Riverlane’s mission is to make quantum computing useful, sooner. From climate change to healthcare, large and reliable quantum computers will help solve some of the world’s important challenges. Riverlane is building the quantum error correction stack to make this happen. It’s a complex problem that requires a range of skills, talent and passion. We’re making remarkable progress and growing fast. About the role We have a fantastic opportunity for an experienced Digital Design Engineer to join us as we build the world’s first quantum error correction (QEC) stack. Don’t have a background in quantum computing? Not a problem! This cutting-edge technology requires a wide range of skills and disciplines, including classical computing skills. You will learn quantum computing along the way. As Senior Digital Design Engineer at Riverlane, you will help develop a multi-FPGA, low-latency, high throughput system that needs to perform complex operations, in a predictable and guaranteed way.You will use your knowledge and expertise to support more junior engineers, interact with software and identify novel solutions to our challenging problems. Our mission is exciting, but complex. It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions. You will thrive in an environment where knowledge sharing and continuous learning are the norm. We are moving fast in a brand new market, where requirements can change as the technology evolves, so the ability to adapt is important. What you will do As a Senior Digital Design Engineer at Riverlane, you will work on one of these key areas: Implementation of QEC decoders on hardware; Implementation of low-latency, high throughput data movement between cards and IPs; or Design of low-latency interfaces to bring data in the systems. In all of the above, you will (often from scratch) design or integrate complex IPs and develop tests, collaborating closely with our Software, Verification and Testing experts to deliver an outstanding product. Requirements
What we need Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10) Experience with ASIC environments ( Proven professional experience in
at least one of
the following areas: Customisation of RISC-V CPUs e.g. addition of new instructions and associated hardware accelerators; Implementation of modern classical decoders on FPGA/ASIC e.g. LDPC, turbo-codes; Architecture of System on Chip solutions with at least one CPU and custom accelerators Proven capability to test, debug and improve complex systems Ability to convert product requirements into technical specifications to document and share your work A curious nature and a passion for learning and continuous improvement Excellent communication skills, with the ability to work both independently and collaboratively as part of a team What you can expect from us A comprehensive benefits package, including annual bonus scheme, private medical insurance, life insurance, a contributory pension scheme (and much more) Equity so that our team can share in the long-term success of Riverlane 28 days annual leave (plus bank holidays) and enhanced family leave A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics, maths and many more) and over 20 different nationalities A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget How to apply
How to apply Please upload a CV and cover letter by clicking here . Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role. We review CVs as we receive them and interview as soon as we have applications that look like a good match (usually within one week). We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. We advertised this role on 7th January 2025 . If you have any queries, please contactâ€¯jobs@riverlane.com . Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. Studies have shown that women tend to apply to jobs if they meet all or almost all of the requirements whereas men apply even if they meet only some of the requirements. If that sounds like you then please apply â€“ we are happy to review your application and let you know if we think you might be a good fit. If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help. Riverlane Ltd
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Cambridge, England, United Kingdom

Sprachkenntnisse

English

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