DFT Engineer

Wer Sie sind

• Language skills: English (C1, fluent)
• Professional experience: min 5 years of experience in chip design industry experience
• Strong System Verilog, RTL Coding skills
• Good understanding of ATE, Wafer bring up debug issues
• Expert skill set in using industry-standard EDA tools in the area of DFT, Synthesis, STA, Simulation tools
• Good understanding of chip level architecture SoC, ASIC
• Knowledge of lab bench SIlicon debug, Characterization% Scripting Knowledge in Python / Shell / TCL etc.,
• Industry Standard DFT architectures/methodologies
• Gate level timing simulations

Ihre Aufgaben

• Driving the DFT architectures, methodologies and tool flows
• Driving the engineering team
• Define the test plan
• Coordinating the functional/structural tests for final/wafer test program development Defining with the team, the HTOL test suits/cycle times/bring up on burnin boards

• Bis zu CHF 110’000
• Lausanne, Vaud, Switzerland

Berufserfahrung

• Other

Sprachkenntnisse

• English
• French