Senior SOC Timing & Clock Network EngineerIntel • Santa Clara, California, United States

Senior SOC Timing & Clock Network Engineer

Intel

Santa Clara, California, United States

Santa Clara, California, United States

Über

Intel Corporation is looking for a Physical Design Timing Engineer to enhance the performance and efficiency of their System-on-Chip (SoC) designs. This role involves conducting SOC level timing analysis, optimizing designs, and developing methodologies for high-performance solutions. The ideal candidate will have substantial experience in static timing analysis and clock network design, showcasing innovative problem-solving capabilities. Competitive compensation includes an annual salary range of $164,470 - $311,890.
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Santa Clara, California, United States

Sprachkenntnisse

English

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