S'INSCRIRE

Cette offre d'emploi n'est plus disponible

XX

Senior SOC Timing & Clock Network Engineer

Intel
  • US
    Santa Clara, California, United States
  • US
    Santa Clara, California, United States

À propos

Intel Corporation is looking for a Physical Design Timing Engineer to enhance the performance and efficiency of their System-on-Chip (SoC) designs. This role involves conducting SOC level timing analysis, optimizing designs, and developing methodologies for high-performance solutions. The ideal candidate will have substantial experience in static timing analysis and clock network design, showcasing innovative problem-solving capabilities. Competitive compensation includes an annual salary range of $164,470 - $311,890.
#J-18808-Ljbffr
  • Santa Clara, California, United States

Compétences linguistiques

  • English
Avis aux utilisateurs

Cette offre a été publiée par l’un de nos partenaires. Vous pouvez consulter l’offre originale ici.