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TPU RTL Design Engineer: High-Speed Interconnects

Google Inc.

Sunnyvale, California, United States

Sunnyvale, California, United States

Über

Google Inc. is seeking a High-Performance ASIC Designer in Sunnyvale, CA. The role involves designing RTL IP for AI and networking accelerators, working closely with various teams to ensure integration and performance. Candidates should possess a Bachelor's degree and at least 4 years of ASIC design experience, along with a deep knowledge of digital systems and high-speed interconnects. Competitive compensation includes a salary range of $138,000 – $198,000 plus bonuses and equity.
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Sunnyvale, California, United States

Sprachkenntnisse

English

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