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Design EngineerCreospan Inc.United States
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Design Engineer

Creospan Inc.
  • US
    United States
  • US
    United States

À propos

Location:
Sunnyvale, CA (Hybrid)
Responsibilities
Perform
RTL and netlist-level power analysis & optimization
Analyze and debug reports from
Synthesis, PD, Timing, and Power flows
Implement
low-power methodologies and UPF
Develop
automation scripts
for report and data analysis
Required Skills
2+ to 10 years
experience in
ASIC Power / Low-Power Design
Hands-on experience with
PrimePower / PTPX or Cadence Joules
Experience with
DC, ICC, VCS, Verdi
Strong scripting skills in
Python / Perl / Tcl
Experience working with
UPF and power estimation flows
Nice to Have
IP / SoC-level power profiling exposure
#J-18808-Ljbffr
  • United States

Compétences linguistiques

  • English
Avis aux utilisateurs

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