System Verilog UVM Design Verification Test EngineerUS Tech Solutions, Inc. • Texas, United States
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System Verilog UVM Design Verification Test Engineer
US Tech Solutions, Inc.
- +3
- +1
- Texas, United States
- +3
- +1
- Texas, United States
About
The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities:
UVM...
Nice-to-have skills
- Ethernet
Work experience
- Embedded
- Hardware
- Electronics Engineering
Languages
- English
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