Company details are confidential
(Closed)
SignupDigital Verification Engineer
- Solutions Engineer+1XXXX
- VerilogSystemVerilog+2XXXX
- Lausanne, Vaud, Switzerland
- Solutions Engineer+1XXXX
- VerilogSystemVerilog+2XXXX
- Lausanne, Vaud, Switzerland
Company
About
Our hiring company is a booming SME/startup active within the semiconductors industry. They created a job offer for a Digital Verification Engineer to integrate into their teams in Lausanne, Switzerland location.
Perks & Benefits
Vacancy
Who you are
- Language skills: English (fluent, C1) min
- Professional experience: min 3 years - 5+ years of experience in semiconductors
- Bachelor's degree in Electronics & Electrical Engineering/Communication System
- Expert in digital design verification, using standardized methodologies (UVM)
- Experience with SystemVerilog Assertions (SVA)
- Would be a plus: an experience with SerDes
Your tasks
- Prepare design verification plan
- Plan and schedule assigned projects
- Utilize latest techniques, tools and technologies for design verification activities
- Maintain design verification environment, track and close design bugs
- Develop design verification methodologies and implement standard debug flows
- Participate in design reviews
Nice-to-have skills
- Verilog
- SystemVerilog
Work experience
- Solutions Engineer
Languages
- English
Are you interested in such a job? Create an account and get matched with opportunitiesCreate an accountIMPORTANT: The only thing you have to do is create your account on TieTalent and THAT'S IT 🙂 + IT'S FREE for talents! YOU WON'T apply for this specific job but rather if there is a match with this opportunity, you will be contacted and have more details about it.