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À propos
Develop UVM-based verification environments including agents, scoreboards, and monitors Create and execute test plans at block, subsystem, and chip levels Collaborate with RTL, DFT, and design teams for debug and validation
Required qualifications:
3+ years of ASIC/SoC verification experience Strong knowledge of SystemVerilog and UVM Experience with VCS/Questa/Xcelium simulators Familiarity with coverage-driven verification methodology Proficiency in scripting languages such as Python, TCL, or Perl
Compétences linguistiques
- English
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