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Design Verification EngineerVirtual Vocations Inc • United States
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Design Verification Engineer

Virtual Vocations Inc
  • US
    United States
  • US
    United States
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À propos

Working remotely during PST hours, the contract Design Verification Engineer will ensure the functional correctness and performance of complex silicon designs by developing UVM-based verification environments and executing comprehensive test plans. Key responsibilities:
Develop UVM-based verification environments including agents, scoreboards, and monitors Create and execute test plans at block, subsystem, and chip levels Collaborate with RTL, DFT, and design teams for debug and validation
Required qualifications:
3+ years of ASIC/SoC verification experience Strong knowledge of SystemVerilog and UVM Experience with VCS/Questa/Xcelium simulators Familiarity with coverage-driven verification methodology Proficiency in scripting languages such as Python, TCL, or Perl
  • United States

Compétences linguistiques

  • English
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