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Analog Circuit Design EngineerIntel Corporation • Santa Clara, California, United States
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Analog Circuit Design Engineer

Intel Corporation
  • US
    Santa Clara, California, United States
  • US
    Santa Clara, California, United States
Jetzt Bewerben

Über

Job Overview
Are you passionate about driving innovation in analog and mixed‑signal circuit design? Join our team to develop groundbreaking power delivery technologies that transform how people interact with technology. As an Analog Circuit Design Engineer, you will be at the forefront of designing and optimizing analog circuits in advanced process nodes. Your contributions will directly influence Intel's mission to deliver high-performance, energy‑efficient products that enrich the lives of people worldwide. Key Responsibilities
Design and develop complex analog and mixed‑signal circuits for advanced CMOS technologies, focusing on power delivery and mixed‑signal IPs. Perform circuit design, simulation, and optimization to meet power, performance, area, timing, and yield goals. Execute analog block floor‑planning and extract chip parameters to ensure robust and efficient designs. Develop and implement test plans to verify circuit designs against microarchitecture specifications. Conduct post‑layout simulations with extracted parasitics and fine‑tune designs to meet required specifications. Collaborate cross‑functionally with architecture, layout, and validation teams to optimize circuit functionality and resolve design challenges. Evaluate experimental test data and iterate designs to improve performance, reduce leakage, and enhance robustness. Qualifications
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 3+ years of relevant experience; or Master's degree with 2+ years of experience; or PhD with no prior experience. Proficiency in analog or mixed‑signal circuit design, including amplifiers, LDOs, PLLs, ADCs, and similar components. Practical knowledge of analog layout techniques, including floor‑planning, matching, shielding, and parasitic optimization. Experience with industry‑standard CAD tools such as Cadence Spectre/AMS Designer/Virtuoso and StarRC for schematic design and simulation. Preferred Qualifications
Expertise in power delivery and power management systems. Hands‑on experience transitioning analog and mixed‑signal circuits from design to layout to silicon prototyping. Familiarity with tools and methodologies for analog validation and debugging. Location
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Massachusetts (Beaver Brook), US, Oregon (Hillsboro), US, Texas (Austin) Business group: The Central Engineering Group (CEG) Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range: $122,440.00–200,340.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Work Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change. EEO Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Recruiting Disclaimer
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
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  • Santa Clara, California, United States

Sprachkenntnisse

  • English
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