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RTL / Physical Design EngineerPersimmons Inc. • San Jose, Arizona, United States
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RTL / Physical Design Engineer

Persimmons Inc.
  • US
    San Jose, Arizona, United States
  • US
    San Jose, Arizona, United States
Jetzt Bewerben

Über

Who we are: Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, we’re on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn’t imagined yet.
Why join us: We’re growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you’re ready to join a world‑class team and play a critical role in making a global impact - we want to talk to you.
What you’ll do: As a Persimmons RTL to PD Engineer, you will be responsible for high‑quality RTL drops to our PD Partners of next‑generation AI silicon. Your primary duties and responsibilities include:
Own RTL‑to‑PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi‑corner environments.
Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign‑off processes—leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
Collaborate closely with RTL design, DFT, and verification teams to manage frontend‑to‑backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
Contribute to advanced post‑DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.
What you bring to the table:
Educational Foundation: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Proven Experience: 3+ years of hands‑on RTL‑to‑PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign‑off checks.
Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL‑level design understanding.
Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI‑assisted automation tools is a strong plus.
Benefits
Competitive salary and benefits package
Flexible PTO
401k
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  • San Jose, Arizona, United States

Sprachkenntnisse

  • English
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