Design Technology Co-Optimization EngineerGoogle Inc. • Sunnyvale, California, United States
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Design Technology Co-Optimization Engineer
Google Inc.
- Sunnyvale, California, United States
- Sunnyvale, California, United States
Über
Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in Physical Design (RTL-to-GDS) or Technology Development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction.
Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools.
Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.
Preferred Qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation.
Experience in Design Technology Co-Optimization (DTCO), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters.
Experience with RTL synthesis and standard cell library optimization.
Expertise in power integrity and reliability analysis and physical verification.
Familiarity with datacenter-class IP blocks, such as high-performance CPU/GPU cores, SRAM arrays, or high-speed interconnects.
About the job In this role, you will shape the future of AI/ML hardware acceleration, drive cutting‑edge TPU technology that powers Google’s most demanding AI/ML applications, and contribute to the innovation behind products loved by millions worldwide. You will leverage design and verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a DTCO Engineer, you will bridge the gap between process technology and product architecture, extract maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures, conduct Place and Route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules, and collaborate with Foundry, IP, and Architecture teams to identify PPA bottlenecks and drive System Technology Co‑Optimization (STCO) initiatives.
Responsibilities
Execute high‑fidelity Place and Route (P&R) experiments to evaluate the PPA impact of advanced process features, library architectures, and design rule variations on datacenter‑class IP.
Drive Design Technology Co‑Optimization (DTCO) by collaborating with foundries and internal technology teams to define optimal metal stacks, track heights, and scaling boosters (e.g., backside power delivery, buried power rails).
Quantify process entitlement through systematic benchmarking of logic and memory macros, identifying bottlenecks in power density and timing closure for next‑generation nodes.
Develop automated physical design methodologies and flows to accelerate technology pathfinding and enable rapid what‑if analysis of emerging transistor architectures.
Influence System Technology Co‑Optimization (STCO) by partnering with Hardware Architects and Circuit Designers to translate process‑level innovations into system‑level performance gains.
Salary and Benefits US: $138,000 – $198,000 (USD) + 15% bonus target + equity + benefits.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
EEO Statement Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.
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Sprachkenntnisse
- English
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