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Senior Physical Design Engineer for Core IP
Intel Corporation
- Hillsboro, Oregon, United States
- Hillsboro, Oregon, United States
Über
Senior Physical Design Engineer – Core IP As a member of the CPU development team, you will play a front seat role in designing the latest core IP that powers cutting‑edge compute processors across client, server, IOTG, and AI domains. The focus is on high‑performance, power‑efficient micro‑processor architecture built on the most advanced process technologies. Your core designs are present in nearly all segments of Intel’s compute roadmap. Responsibilities
Synthesize and place & route using industry‑standard tools for high‑speed CPU core design. Perform all aspects of the design flow: logic synthesis, place & route, FEV, power, timing, quality checks, and design closure. Develop strategies to deliver reproducible design convergence results. Create and refine synthesis flow for the project team. Recommend better design method practices to enable improved synthesis convergence. Collaborate across complex decision spaces, building implementation plans, monitoring key indicators, and communicating resource needs and scoping risk to deliver value on schedule. Maintain strong verbal and written communication and collaboration skills. Qualifications
Minimum Qualifications
Bachelor’s degree in Computer, Electrical Engineering, or related field with 10+ years of relevant experience. Or Master’s degree in the same field with 5+ years of relevant experience. 10+ years of experience with integrated circuit design tools (e.g., Synopsys/Cadence) including logic synthesis, place & route, static timing analysis, design closure, and PV convergence. Experience in chip physical design verification: formal equivalence, timing, electrical rules, DRC/LVS, noise, and electro‑migration checks. Proficiency in scripting with an interpreted language (minimum TCL and at least one additional language such as Perl, Python, or Ruby). Demonstrated success in synthesis of a digital logic block that was integrated into a large SoC or IP. Preferred Qualifications
Deep knowledge of physical design best practices: floor‑planning, routing techniques, clock distribution, static timing analysis, noise analysis, and reliability verification. Experience with RTL‑to‑GDS methodologies and formal equivalence. Proficiency with Synopsys tool suite (Fusion Compiler, ICC2, PrimeTime) or Cadence tools (Genus/Innovus). Ability to perform CPU‑level timing analysis and optimization to meet functional and performance requirements. Experience generating and verifying timing constraints and addressing timing violations at the chip or block level for CPU cores. Collaboration with the clocking team and full‑chip designers to balance timing fixes, power delivery, clocking, and partitioning. Employment Details
Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Business group: Intel Benefits
Annual Salary Range: $164,470 – $269,100 USD. The range represents the minimum and maximum target compensation in the US. Pay is determined by work location and factors such as skills, experience, and education. The total compensation package includes competitive pay, stock bonuses, and benefits such as health, retirement, and vacation. EEO Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Sprachkenntnisse
- English
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