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IVR / 3DIC Design Flow Engineer (7102)

TSMC

San Jose, Arizona, United States

San Jose, Arizona, United States

Über

Overview We are seeking a highly skilled and motivated Analog & Mixed‑Signal / 3DIC Design Flow Engineer to lead development of Integrated Voltage Regulator (IVR) flows for advanced 3DIC technologies. This role is critical to enabling efficient power delivery for AI and HPC workloads. The engineer will design and implement 3DIC‑compatible analog flows by collaborating with third‑party EDA tool vendors, analog/digital/3DIC design teams, model teams, advanced/3DIC technology teams and worldwide customers, and drive system‑level integration into GPU and SoC platforms. The position requires deep expertise in analog/mixed‑signal design, 3DIC integration, and EDA tool enablement. Responsibilities Develop AMS/3DIC design flows compatible with TSMC PDKs, focusing on IVR integration. Construct schematic and simulation methodologies for 3DIC analog design. Collaborate with EDA vendors to enable and enhance tool features, building customized design scripts. Deliver flows optimized for large‑scale GPU/SoC integration to support customer tape‑outs. Work with cross‑functional teams (3DIC, analog, digital, model, process R&D) to define specifications and requirements. Stay current with emerging trends in IVR, AMS, and 3DIC to shape future design methodologies. Required Skills Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related field. 15+ years of proven experience in analog and mixed‑signal design with PMIC/IVR focus. Strong knowledge of 3DIC design integration and analog flow development. Proficiency with Cadence, Synopsys, Ansys and other AMS/3DIC EDA tools (schematic, layout, simulation, extraction). Strong analytical and problem‑solving skills for design and CAD issues. Effective collaboration and communication skills across global teams. Preferred Skills Programming skills in Python, Perl, SKILL, TCL, or Shell for design automation. Experience with Verilog, Verilog‑A, AMS or other chip behavior modeling. Knowledge of PDN extraction, SI/PI, thermal, and reliability analyses (Totem, Voltus‑Fi, Redhawk, Celsius, etc.). Exposure to API development for EDA tool integration. Knowledge of machine learning techniques for design optimization. Location San Jose, CA or Hsinchu, Taiwan. Diversity Statement TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, protected veteran status, genetic information, or any other characteristic protected by applicable law. If you require accommodation due to a disability during the application or recruiting process, notify G_ACCOMMODATIONS@TSMC.COM. Pay Transparency At TSMC, this role typically pays a base salary between $153,000 and $250,000 per year. The range reflects the minimum and maximum target for new hires. Actual pay may vary. Compensation may differ by location and local market practices.
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San Jose, Arizona, United States

Sprachkenntnisse

English

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