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Mask Design Engineer
STEM Xpert
- Hillsboro, Oregon, United States
- Hillsboro, Oregon, United States
Über
We strongly believe: "If something cannot be measured, it cannot be managed." TEKWISSEN™ measures all of these processes and applies corrective interventions to manage the quality process at its core.
We are an Equal Employment Opportunity Employer M/F/V/D
Recognitions:
2015 - America’s Fastest Growing Company by Inc.com
2015 - SPARK FastTrack Award from Ann Arbor SPARK
2015 - Honoree of Diversity Focused Company by Corp! Magazine
2014 - America’s Fastest Growing Company by Inc.com
2014 - Michigan 50 Companies to Watch
2014 – DiSciTech Award in Technology by Corp! Magazine
2014 - DiSciTech TECHNOLOGY Company of the year by Corp! Magazine
2014 - SPARK FastTrack Award from Ann Arbor SPARK
Specialties:
Enterprise Solutions
Web Development
Data Warehousing
Systems Integration
IT Security
Storage Technologies
Development and Delivery
Business Intelligence
Telecommunications
Consulting and Planning
Network design, Implementation & Administration
Job Description Mask Design
Location: Hillsboro, OR
Duration: Long Term
Job Description:
Manditory skills:
1. 14nm
2. Genesys, Genoa
3. Voltage regulators, LDO
At least 4 – 8 years’ experience in understanding and independent handling of various Analog and Mixed Signal blocks such as LDO, Switching Regulators, Data Converters, PLL, SerDes, LVDS and top level layout integration of AMS blocks.
Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 14nm, 22nm, 16nm FinFET technologies.
Experience in Genesys / Genoa layout editor, Aapr flow, Helix, etc.
Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC, etc.
Deep understanding of reliability analysis in layout like EM, IR drop, latch‑up, ESD etc using Apache tools.
Should have good knowledge of CMOS, FinFET process and fabrication.
Knowledge of scripting languages such as Perl/Tcl and Skill is a plus.
Full‑chip integration and verification experience.
Good team player with excellent communication skills, interfacing with the circuit team.
Layout design, Verification, Post‑layout fixes and sign‑off of high performance of Analog and Mixed Signal blocks, and IO / High Speed IO blocks.
Mask Design team lead for the client engagement.
Interface with the Circuit Design team at Onsite.
Proficiency in using industry standard EDA tools like Cadence (Virtuoso‑L, Virtuoso‑XL, PVS & QRC), Mentor Graphics (Calibre & XRC), Hercules.
Additional Information #J-18808-Ljbffr
Sprachkenntnisse
- English
Hinweis für Nutzer
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