Senior R&D

Synopsys

Sunnyvale, California, United States

Sunnyvale, California, United States

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Über

Senior R&D Engineer Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You have spent time deep in the physics of how signals move through silicon, and you know that the difference between a chip that works at speed and one that doesn't often comes down to parasitic effects most people never see. Maxwell's equations are not abstract theory to you; they are the foundation of how you think about interconnect behavior at 3nm and below. You are comfortable moving between electromagnetic theory and production C++ code. You can derive a quasi-static model in the morning and spend the afternoon optimizing a data structure that must handle billions of elements without falling over. When a foundry sends you a challenging new process corner or a customer describes a signoff failure in a CPU design, you do not panic, you dig in, reproduce it, and figure out what the model is missing. Building things that must be right matters to you. Not approximately right for a demo, correct when someone tapes out a chip worth millions of dollars. You ask hard questions about accuracy versus runtime tradeoffs, and you care about both. You know that an extraction model that adds 10% runtime but catches a critical coupling issue is worth it, and you can articulate why to both engineers and product managers. At Synopsys, you will work on StarRC, the tool that sets the standard for parasitic extraction across the industry, and what you build will directly affect whether advanced designs close on schedule. What You'll Be Doing
Research, design, and implement new transistor level extraction capabilities for StarRC, focusing on modeling accuracy for FinFET and gate-all-around devices at 3nm, 2nm, and beyond Develop parasitic models for interconnect capacitance, inductance, and resistance using pattern-matching techniques and field solver methods Apply computational electromagnetics principles to solve complex extraction problems for advanced process nodes Design efficient algorithms and data structures in C++ that handle massive layout datasets while maintaining extraction accuracy and runtime performance Collaborate with engineers across layout, simulation, timing, and physical verification teams to ensure StarRC integrates seamlessly into customer signoff flows Work directly with foundries and customers to resolve extraction challenges in CPU designs, 3D IC systems, and advanced packaging structures
The Impact You Will Have
Enable accurate signoff for chips at the most advanced process nodes, directly affecting whether billion-dollar designs can tape out on schedule Improve extraction runtime and capacity so customers can close timing on larger, more complex SoCs without sacrificing accuracy Delivering capabilities that help foundries and design teams understand parasitic effects in new process technologies before they become yield problems Strengthening StarRC's position as the gold standard extraction tool by solving problems competitors cannot Help customers across CPU, AI accelerator, and memory design teams achieve first-pass silicon success by catching parasitic issues early Shape the technical direction of extraction technology through direct collaboration with leading foundries and design houses
What You'll Need
MS or PhD in Electrical Engineering, Computer Science, or Computer Engineering with 1+ years of relevant EDA or CAD software development experience Strong background in computational electromagnetics, including experience with full-wave or quasi-static EM modeling, Maxwell's equations, and numerical methods such as FEM, BEM, or MoM Hands-on experience with transistor level parasitic extraction or modeling Proficiency in C++ programming, algorithm design, and data structures for performance-critical software systems Understanding how parasitic effects impact circuit performance and signoff, experience with LVS, extraction, or circuit simulation flows is a plus Familiarity with field solver technology or transmission line analysis is a plus
Who You Are
You can explain a complex electromagnetic modeling tradeoff to a product manager in two sentences and then debug a numerical stability issue in a solver implementation You do not wait for perfect specs, when a foundry provides incomplete process data, you identify what is missing, ask the right questions, and build a model that works You care about correctness at scale, an algorithm that works on a test case but crashes on a real customer design is not a solution You are comfortable being wrong in a design review if it means the team catches a problem before it ships You can switch between deep technical work and customer-facing problem solving, some days you are debugging FEM convergence issues, other days you are on a call with a design team in Asia
The Team You'll Be Part Of You will be a member of a high performing R&D team contributing to the development of StarRC, the EDA industry's gold standard for parasitic extraction. The team works on modeling physical effects for advanced process technologies, including FinFET at 7nm, 5nm, 3nm, 2nm, and beyond. You will collaborate closely with other product developers across layout design, simulations, timing, reliability verification, and physical verification. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Sunnyvale, California, United States

Sprachkenntnisse

English

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