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Senior Chiplet Package Design Engineer (2.5D / 3D Integration)
Rapidus Corporation US
- United States
- United States
Über
Chiplet Package Design Engineer
to drive the development of advanced packaging solutions for next-generation semiconductor products. This role focuses on
2.5D and 3D heterogeneous integration , enabling high-performance computing, AI, networking, and advanced SoC platforms. The candidate will work cross-functionally with silicon design, system architecture, manufacturing, and OSAT partners to deliver cutting-edge chiplet-based packaging solutions. Locations:
Albany, NY (USA) / Santa Clara, CA (USA) / Tokyo (Japan) / Chitose (Japan) Employment Type:
Full-time Department:
Design Enablement / Advanced Packaging Technology About Rapidus Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry. Key Responsibilities Lead the
design and development of 2.5D/3D package architectures
(e.g., interposer-based, fan-out, and 3D stacking) Define and optimize
chiplet integration strategies , including die partitioning, interface definition, and interconnect topologies Develop
package layout and routing
for high-speed/high-density interconnects (e.g., HBM, UCIe, PCIe, SerDes) Perform and guide
signal integrity (SI), power integrity (PI), and thermal analysis Collaborate with silicon teams on
bump/pad design, floorplanning, and co-design methodologies Drive
package-substrate co-design
including material selection and stack-up definition Interface with
OSATs and foundries
for manufacturability, yield improvement, and cost optimization Support
DFx (DFM, DFT, DFA)
and reliability validation (warpage, stress, electromigration) Contribute to
package technology roadmap
for advanced nodes (2nm and beyond) Participate in
bring-up, validation, and failure analysis
of packaged devices Required Qualifications B.S. or M.S. in Electrical Engineering, Mechanical Engineering, Materials Science, or related field 5+ years of experience in
semiconductor package design , especially advanced packaging Hands-on experience with
2.5D/3D packaging technologies
(e.g., silicon interposer, TSV, hybrid bonding) Strong knowledge of
high-speed interfaces
and package-level SI/PI considerations Experience with industry-standard tools (e.g., Cadence Allegro Package Designer, Sigrity, Ansys HFSS, RedHawk-SC Electrothermal) Understanding of
package manufacturing processes and OSAT ecosystem Ability to work in cross-functional and global teams Preferred Qualifications Experience with
chiplet architectures and standards
(e.g., UCIe) Knowledge of
HBM integration, AI accelerators, or HPC systems Experience with
thermal/mechanical simulation tools
(e.g., Ansys Mechanical, Icepak) Familiarity with
advanced substrates (ABF, glass core, fan-out RDL) Experience in
co-design with silicon (die-package-system co-optimization) Knowledge of
yield analysis and reliability modeling Japanese language skills (for collaboration with Japan-based teams) What We Offer Opportunity to work on
cutting-edge chiplet and heterogeneous integration technologies Collaboration with global teams across the US and Japan Exposure to next-generation nodes (2nm and beyond) Competitive compensation and career growth opportunities Benefits Comprehensive Health, Dental and Vision coverage, fully at company's expense (no deductibles) 401k with no employer match
Sprachkenntnisse
- English
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