Senior Design Verification Engineer | Upto $175/hrMercor • Saint Paul, Illinois, United States
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Senior Design Verification Engineer | Upto $175/hr
Mercor
- Saint Paul, Illinois, United States
- Saint Paul, Illinois, United States
Über
Position Details RTL Design Engineer
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week
Role Responsibilities
Evaluate and enhance AI model training for digital chip design and verification.
Design and implement RTL components using Verilog/SystemVerilog.
Develop and maintain ASIC design flows including lint, synthesis, and timing analysis.
Collaborate with architecture, verification, and implementation teams to ensure seamless integration.
Utilize EDA tools for simulation, waveform debug, and coverage analysis.
Work independently and asynchronously to meet project deadlines and improve AI model performance.
Qualifications Must-Have
3–10 years of experience in digital RTL design or design verification.
Strong proficiency in Verilog/SystemVerilog and UVM.
Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
Experience with ASIC design flows and EDA tools.
Familiarity with leveraging LLM-based tools for chip design and verification workflows.
Preferred
Knowledge of AMBA protocols (AXI, AHB, APB).
Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
Exposure to formal verification or SV/UVM-based design verification.
Start Date
Week of 04/23; applications reviewed on a rolling basis.
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Sprachkenntnisse
- English
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