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Digital Verification Engineer

Lausanne, Switzerland

Our hiring company is a booming SME/startup active within the semiconductors industry. They created a job offer for a Digital Verification Engineer to integrate into their teams in Lausanne, Switzerland location.

Your tasks

  • Prepare design verification plan
  • Plan and schedule assigned projects
  • Utilize latest techniques, tools and technologies for design verification activities
  • Maintain design verification environment, track and close design bugs
  • Develop design verification methodologies and implement standard debug flows
  • Participate in design reviews

Your profile

  • Language skills: English (fluent, C1) min
  • Professional experience: min 3 years – 5+ years of experience in semiconductors
  • Bachelor’s degree in Electronics & Electrical Engineering/Communication System
  • Expert in digital design verification, using standardized methodologies (UVM)
  • Experience with SystemVerilog Assertions (SVA)
  • Would be a plus: an experience with SerDes


This career opportunity is based in the Lausanne, Switzerland.

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YOU WON’T apply for this specific position but rather if there is a match with this opportunity, you will be contacted and have more details about it.