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Lead SOC Design Engineer - RTL, Timing & VerificationCadence Design SystemsSan Jose, Arizona, United States
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Lead SOC Design Engineer - RTL, Timing & Verification

Cadence Design Systems
  • US
    San Jose, Arizona, United States
  • US
    San Jose, Arizona, United States

À propos

Cadence Design Systems in San Jose is seeking a Principal Design Engineer to implement and verify complex System-On-Chip (SOC) designs. This leadership role involves managing teams and working with advanced technologies while ensuring successful tape-out processes. The ideal candidate should have a degree in Electrical Engineering and extensive experience with Cadence tools and industry-standard interfaces. Cadence values creativity, innovation, and employee well-being, offering a competitive salary and comprehensive benefits including a 401(k) plan.
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  • San Jose, Arizona, United States

Compétences linguistiques

  • English
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