S'INSCRIRE

Offres d'emploi

Trouvez des postes près de chez vous, sur site, hybrides ou à distance.
  • Emplois similaires à : Senior Power Integrity & Chip Design Engineer
XX
Senior CPU RTL Design Engineer – Power ManagementIntel Corporation • Austin, Texas, United States
Postuler Maintenant
XX

Senior CPU RTL Design Engineer – Power Management

Intel Corporation
  • US
    Austin, Texas, United States
  • US
    Austin, Texas, United States
Postuler Maintenant

À propos

Job Overview
Join Intel’s CPU Design Team within the Silicon & Platform Engineering (SPE) Group. As a Senior CPU RTL Design Engineer – Power Management, you will help architect and deliver next‑generation, power‑efficient, high‑performance processors. What You’ll Do
Define, design, and implement CPU microarchitecture features. Develop and deliver RTL (SystemVerilog/Verilog) for CPU IP blocks. Drive power, performance, and area (PPA) optimization, focusing on power‑aware RTL design and energy‑efficient architectures. Design and validate multi‑clock domain and CDC solutions. Contribute to CPU power management features, including dynamic voltage and frequency scaling (DVFS), power/thermal management, reset flows and power state transitions (P/C states). Debug complex RTL and collaborate with verification teams. Partner with SoC integration teams for full‑chip delivery. Contribute to design methodology improvements and scalability. Qualifications
Minimum: Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related field with 9+ years of relevant experience, or Master’s degree with 7+ years. Experience with power management concepts (DVFS, power states, budgeting). Experience in low‑power / power‑aware CPU or SoC RTL design, RTL development (Verilog/SystemVerilog). Debug and system‑level design understanding. Preferred: experience in multi‑clock domain / CDC design. Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language. Experience with high‑speed circuit design and optimization, specifically for datapath, circuits, and arrays. Familiarity with circuit planning and timing convergence processes. Ability to leverage broad understanding of CPU architecture to deliver impactful solutions. Proficient with static timing analysis, UPF and lint checks. Attributes
Ownership & Accountability – operates independently with minimal guidance. Depth over keywords – demonstrates hands‑on expertise. Problem‑solving rigor – able to debug and resolve complex design issues. Collaboration mindset – works effectively across cross‑functional teams. Technical leadership – influences design decisions and drives best practices. Bias for action & urgency – maintains strong execution pace in fast‑moving environment. Compensation
Annual Salary Range: $164,470.00 – $269,100.00 USD (US location). Pay is determined by location and additional factors including skills, experience, and education. Benefits
Competitive pay, stock bonuses, health, retirement and vacation benefits. EEO Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
#J-18808-Ljbffr
  • Austin, Texas, United States

Compétences linguistiques

  • English
Avis aux utilisateurs

Cette offre provient d’une plateforme partenaire de TieTalent. Cliquez sur « Postuler maintenant » pour soumettre votre candidature directement sur leur site.