À propos
Staff Engineer (Design Verification)
Location:
San Diego, CA Duration:
12+ Month Contract
Role Summary
Design Verification Engineer for high-speed mixed-signal IP (PCIe, USB, MIPI, DDR, etc.), supporting full lifecycle from pre-silicon to post-silicon for 5G, AI/ML, IoT, and automotive applications.
Top Skills (Must Have)
SystemVerilog/UVM verification methodology
ASIC simulation/formal tools (VCS, Xcelium, Questa, JasperGold, VCFormal)
High-speed protocols: PCIe, USB, MIPI, DDR, UFS
SVA assertions, debugging, coverage closure
Strong verification/testbench development experience
Key Responsibilities
Define pre/post-silicon test plans based on specs
Develop testbenches (SystemVerilog/UVM, mixed-signal, low power)
Write assertions (SVA), testcases, coverage models
Perform debugging and ensure coverage closure
Collaborate with design, analog, SoC, and integration teams
Support post-silicon validation
Preferred Skills
Low power (UPF), formal & gate-level verification
Mixed-signal IP verification (SerDes, PLL, ADC/DAC, sensors)
Scripting (Python/Perl)
VIP development for SerDes/PHY
Qualifications
Bachelor’s/Master’s in EE/CE or related
5+ years ASIC design verification experience
Compétences linguistiques
- English
Avis aux utilisateurs
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