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À propos
Shift: Shift 1 (United States of America)
Primary Location: US, Arizona, Phoenix
Additional Locations: US, California, Folsom; US, Texas, Austin
Job Description The world is transforming – and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow’s technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful.
Responsibilities
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimizes design to improve product level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Qualifications Minimum Qualifications
Master’s Degree in Electrical or Computer Engineering, Computer Science, or a STEM related field with 6+ years of experience – OR – Bachelor’s Degree in Electrical or Computer Engineering, Computer Science, or a STEM related field with 9+ years of experience.
6+ years experience with APR tools, either Synopsys or Cadence.
6+ years experience with static timing analysis (STA).
6+ years experience with TCL, Python or Perl programming.
Preferred Qualifications
Experience in all aspects of physical design using Synopsys or Cadence tools.
Strong background with industry standard tools for synthesis, place and route, and tape out flows.
Technical expertise in physical design verification methods such as timing signoff, formal verification, and low power static signoff.
The ideal candidate will also have excellent communication, teamwork, and problem‑solving skills.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Annual Salary Range: $164,470.00-269,100.00 USD
This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.
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Compétences linguistiques
- English
Avis aux utilisateurs
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