Cette offre d'emploi n'est plus disponible
Senior Verification Engineer - RTL/UVM for ASICs
jobtraffic
- Ireland
- Ireland
À propos
Find out more about this role by reading the information below, then apply to be considered.
This position involves applying advanced verification methodologies and developing testbenches to ensure high-quality deliverables.
The ideal candidate should have at least 3 years of related experience, a strong background in UVM and SystemVerilog, and proficiency in Python. xcfaprz
This role offers the opportunity to work on cutting-edge projects in a dynamic environment.
#J-18808-Ljbffr
Compétences linguistiques
- English
Avis aux utilisateurs
Cette offre a été publiée par l’un de nos partenaires. Vous pouvez consulter l’offre originale ici.