Principal Verification Engineer

Principal Verification Engineer (Memory)

Cork or Dublin

Design Engineering Director

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial, and health. The Cadence Silicon Solutions Group (SSG) develops leading‑edge IP for a variety of high‑tech markets, enabling customers to tackle IP‑to‑SoC development in a system context, reduce time to volume, and focus on product differentiation.
This is an opportunity to join a development team designing state‑of‑the‑art DDR memory controllers for a wide range of applications, including datacenter, edge computing, automotive, and AI. The Principal Verification Engineer will be based in Cork, Dublin, or Galway as part of an experienced Controller IP Team with long established Controller development sites in Europe, the US, and India.

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• Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage.
  
• Development of UVM‑SV Scoreboards for self‑checking regressions.
  
• Development of Functional Coverage as part of Metric‑Driven Verification Environments.
  
• Development of SystemVerilog Assertions for use in Formal and Simulation Environments.
  
• Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
  
• Creation and Management of Automated Regression Environments, e.g., Jenkins.
  
• Participation in Technical Review Meetings and Checklist Reviews as part of ISO‑9001.
  
• Close collaboration with Design Engineers to debug complex test scenarios.
  

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• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline.
  
• 10–15 years of experience in the microelectronics/EDA industry.
  
• Experience with Verilog RTL Design (essential).
  
• Experience with Metric‑Driven Verification (MDV) (essential).
  
• Excellent oral and written English (essential).
  
• Self‑motivated with excellent planning, interpersonal, and communication skills.
  

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• Experience with front‑end design tools covering LINT, Synthesis, CDC Analysis (preferred).
  
• Experience with quality processes such as ISO‑9001 & ISO‑26262 (preferred).
  
• AXI and/or CHI experience (highly desirable).
  

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. xcfaprz All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, veteran status, disability, or any other protected class.