À propos
Pay Range: $90hr - $125hr
We are seeking an experienced FPGA/VHDL Design Engineer to develop and implement complex algorithms targeting ASICs and FPGAs. The ideal candidate will be proficient in VHDL and have hands-on experience with Xilinx FPGAs and the Vivado design suite. This is a mid to senior-level role requiring expertise in architecture, design, verification, synthesis, and static timing analysis. Prior exposure to high-speed communication protocols and embedded software is a plus. Requirement/Must Have:
t least 3 years of experience implementing complex algorithms on ASIC/FPGAs Proficiency in VHDL with 5+ years of hands-on experience Hands-on experience with Xilinx FPGA design using Vivado Experience with complete FPGA design cycle: architecture, design, verification, synthesis, and static timing analysis (STA) Strong analytical and debugging skills Excellent verbal, written, and presentation skills Bachelor of Science in Electrical Engineering or Computer Science (Master's preferred) Should Have:
Experience working with high-speed protocols such as PCIe, TCP/IP, and Ethernet Prior hands-on work beyond just IP instantiation with Ethernet protocol Familiarity with Mentor Graphics EDA tools: CDC, Lint, Asynchronous Clock (AC), Reset Domain Crossing (RDC) Nice-To-Haves (Hard Skills):
High-Level Synthesis (HLS) with Vivado Embedded software development in C++ with object-oriented programming Experience with System Verilog Assertions (SVA)
Compétences linguistiques
- English
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