Principal Logic Design Engineer

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About the Role

Intel's multiprotocol SerDes design team is hiring in our Toronto office to ensure continued support of some of the world's most versatile next-generation products. We have a long track record of silicon success over multiple technology nodes. Supporting the team in Toronto, we are hiring a technically experienced Principal Logic Design Engineer.

The key responsibilities of this person include the following:

• Logic design, register transfer level (RTL) coding, analog circuit behavioral modeling and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
• Participating in the definition of architecture and microarchitecture features of the block being designed.
• Applying various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviewing the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Supporting SoC customers to ensure high quality integration and verification of the IP block.
• Driving quality assurance compliance for smooth IP SoC handoff.
• Create design documentation

The Logic Design Engineer should possess the following attributes:

• Excellent communication: Expected to drive clarity across partners, managers.
• Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can.
• Strong analytical and problem-solving skills with the skills to independently draw conclusions.

Required Skills and Experience:

• Mixed-signal design, specifically High-Speed SerDes design and architecture
• Experience with PCS/FEC, gearbox, equalization, and clocking structures
• Experience with pipelining, retiming, clock domain crossings (CDC), and latency optimization
• Experience with post-silicon validation and support of High-Speed SerDes IP
• Experience working with automated Place-and-Route (APR) teams on synthesis, STA constraints, timing closure, and DFT considerations
• Knowledge of FFE/DFE filters, CDR DSP blocks, interpolation/decimation, and adaptive algorithms
• Reading and interpreting technical specifications to develop microarchitecture and implement RTL design in SystemVerilog
• Excellent communication: Expected to drive clarity across partners, managers.
• Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can

Preferred Skills and Experience:

• Familiarity with AXI, AHB, and APB protocols
• DSP-based CDR design, Forward Error Correction (FEC) coding, hardware/software co-simulation, power/performance optimization, and machine learning-assisted DSP tuning
• Experience with PCIe, Ethernet (100G/400G/800G), CEI, USB, or similar standards
• Scripting proficiency in at least one interpreted language (e.g., TCL, Perl, Python, Ruby)
• Knowledge of UVM/testbench architecture, constrained random testing, and functional coverage

• Bachelor's in electrical/computer engineering and 10+ years of experience -OR- Master's degree with 6+ years of experience
• Deep experience in Mixed signal design specifically High Speed SerDes design and architecture

Annual Salary Range for jobs which could be performed in Canada

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

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