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Senior ASIC (Front-End) Design EngineerEthernovia • United States
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Senior ASIC (Front-End) Design Engineer

Ethernovia
  • +3
  • +9
  • US
    United States
  • +3
  • +9
  • US
    United States
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À propos

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we’re inventing the future of automobile’s communication! We are transforming automobiles’ communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities. We bring together, accelerate, and unify the car’s cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services.With talented employees on 4 continents, we have filed > 50 patents to date.Join Ethernovia’s team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car.Senior ASIC Front-End Design EngineerSummary:As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.Work with system architects, software, hardware, and verification engineers to plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.You will be on the leading edge of the development and definition of advanced, high-performance custom silicon that embodies functions from a wide range of protocols, algorithms, and applications.Expected to flesh out product definitions with precise specifications of: an ASIC's internal and external interactions, data flow, processing algorithms across a number of disciplines, resource management, and software interfaces.You will be a trusted self-starter who can work with very little guidance or oversight.This position is located in: United States - RemoteKey Qualifications:BS and/or MS in Electrical Engineering, Computer Science, or related fieldMinimum 10+ years of ASIC RTL design and/or architecture experienceProven track record with the development of complex SoCsStrong understanding of digital design fundamentals and methodologiesIn-depth knowledge of Verilog/System Verilog and simulation tools.Self-motivated and able to work effectively both independently and in a teamAdditional Success Factors:Experience in any of the following areas:Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)Video standards, protocols, processingDigital signal processing filtersPerl, TCL, C/C++, MakePersonal Skills:Collaboration across multidisciplinary and international teams.What You Can Expect From Ethernovia:Technology depth and breadth expansion that can’t be found in a large companyOpportunity to grow your career as the company growsPre IPO stock optionsCutting edge technologyWorld class teamFlexible hoursMedical, dental and vision insurance for employeesFlexible vacation time to promote a healthy work-life balancePaid parental leave to support you and your familySalary Range:The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. We would not anticipate that the individual hired into this role will be at or near the top half of the range provided, but the decision will be dependent on the factors of each individual case. The annual salary range for this position is $180,000 - $230,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.Apply for this job #J-18808-Ljbffr

Compétences idéales

  • Algorithms
  • Hardware
  • Networking
  • PCIe
  • Perl
  • Security
  • TCL
  • TCP/IP
  • Verilog
  • United States

Expérience professionnelle

  • Embedded
  • Hardware
  • Electronics Engineering

Compétences linguistiques

  • English
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