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Design For Test - DV Engineer
AMD
- Cambridge, England, United Kingdom
- Cambridge, England, United Kingdom
À propos
The Role We are seeking an experienced DFT Design Verification (DFT DV) engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and experience in DFT and DV methodologies, particularly in the context of CPU core design and development.
Key Responsibilities
Verify advanced Design for Test (DFT) functions such as Scan, Memory BIST, JTAG/IJTAG/P1500 and partitioned test structures.
Work with architects, designers and post‑silicon teams to develop detailed test plans for new features.
Develop test benches and build directed and random verification tests to verify DFT implementation at RTL/gate‑level and provide timely feedback to designers.
Debug test failures to determine root causes; work with RTL and firmware engineers to resolve design defects and correct any test issues.
Improve code/functional coverage to achieve design verification metrics defined for project milestones.
Coordinate with test engineers and generate high‑quality test patterns and DV tests to run on silicon.
Act as a bridge between test engineers and design teams in debugging silicon failures and support triage until resolution.
Collaborate with other DFT‑DV team members across sites and time zones to innovate and improve DV methodologies/flows, develop unified DFT‑DV strategies and share best practices.
Mentor and coach junior engineers.
Preferred Experience
Solid DFT verification skills using Verilog, System Verilog, C/C++/Assembly, OOP, Perl/Python etc.
Good understanding of Design for Test architecture and methodologies (e.g., JTAG, IJTAG, Core Test, Scan, MBIST).
Strong skills in Verilog simulation and debugging using simulation tools (e.g., VCS).
Experience with version control systems such as Perforce, Git.
Write, maintain and enhance scripts using Perl, Python or other scripting languages.
Exposure to AI capabilities in DV workflow.
Experience in UVM, Formal Verification, Assertion‑Based Verification flows.
Experience developing UVM based verification frameworks and testbenches, processes and flows and automating workflows in a distributed compute environment.
Experience with high‑performance, power‑efficient designs.
Knowledge of advanced DFT components such as SSN, SSH, Test Compression, OCC.
Knowledge of MBIST implementation flows and experience in MBIST DV.
Knowledge of ATPG pattern verification and gate‑level simulation flows using Synopsys VCS and Verdi or other state‑of‑the‑art EDA tools.
Exposure to post‑silicon testing and tester pattern debug.
Strong problem‑solving and debug skills across design hierarchies.
Good communication skills and ability to work in a worldwide team environment.
Exposure to leadership or mentorship.
Academic Credentials
Bachelor’s or Master’s degree in Computer / Electrical / Electronics Engineering.
Benefits AMD benefits at a glance.
Equal Opportunity Statement AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Responsible AI Policy AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
Vacancy Status This posting is for an existing vacancy.
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Compétences linguistiques
- English
Avis aux utilisateurs
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