FPGA Design Engineer

Stefanini Group is hiring Stefanini is looking for FPGA Design Engineer with Radio experience (Onsite Role) in Ottawa, Ontario, Canada For quick apply, please contact Rahul Kumar Ph: / Total Days Total PTO(See Below the bifurcation)   * 10 Days PTO( 80 Hours of PTO  - Accrual Basis) *  9 Holidays on average throughout the year *  3 Personal Days   Ideal Candidate: FPGA designer engineer with Radio experience. Working with 4G/5G Radios. 7+ years of experience Heavy System Verilog and RTL experience.  They DO NOT USE VHDL.  Tools: Altera Quartus. Matlab/Simulink for modeling Axi and Ethernet protocol experience are more important than other high-speed experience.    Responsibilities: 

• Works on unusually complex problems and provides highly innovative solutions Uses independent judgment to accomplish goals and objectives 
• Has insight into industry trends and communicates vision to guide organizational strategy and long-range planning 
• Lends research and contributes to evaluations, project plans and budgets for new products or updates existing products 
• Acts as consultant on critical projects that impact long term organizational goals and objectives 
• Leads teams, gives technical guidance and communicates with senior management on progress Identifies or creates solutions that are likely to contribute to the development of new company concepts 
• Expected to set standards and achieve cost targets for product cost through proper design choices, component selection or supplier selection 
• Demonstrated expertise in competitive analysis 
• May actively seek customer input and take responsibility for internal and external customer situations 
• Determines requirements and functional specifications for entire system, under only consultative direction.

What You'll Do: Design & Architecture:

• Develop FPGA IP architecture for 4G/5G Radio Units.
• Contribute to system-level design aligned with 3GPP and O-RAN Alliance specifications.
• Implementation:
• Implement complex RTL blocks (Verilog/SystemVerilog) and integrate into larger systems.
• Optimize FPGA resource utilization and ensure timing closure.

• Define and execute verification plans using UVM and advanced techniques.
• Perform simulation and system-level FPGA validation.

• Work closely with Radio Unit development teams for seamless integration.
• Partner with software teams to ensure hardware-software interoperability.
• Mentor junior engineers and participate in technical reviews.

• Proven experience in FPGA design and RTL development.
• Expertise in NR/LTE/eCPRI/CPRI/PTP protocols and signal processing.
• Familiarity with JESD204B/C, Ethernet, PCIe, AXI, and high-speed SERDES.
• Tools: Quartus, Vivado, MATLAB/Simulink, HDL Coder.
• Knowledge of UVM and verification methodologies.
• Strong understanding of 4G/5G Radio architecture and O-RAN ecosystem.
• Experience with Git/GitHub and version control workflows.

• 7+ years of FPGA design experience in wireless or high-speed systems.
• Experience in high-volume wireless products and IP development.
• Contributions to standards bodies or technical forums (O-RAN, 3GPP).