DSP / Digital Engineer

Location: Markham, Ontario (Onsite)

Employment Type: Full-Time

Sonele brings together transducer innovation and electronics to deliver advanced ultrasound solutions. Our digital platforms integrate high-speed data acquisition, FPGA/DSP processing, and robust embedded software pipelines.

The DSP/Digital Engineer develops FPGA and digital processing pipelines for ultrasound acquisition and beamforming, enabling high-throughput, low-latency data paths from front‑end electronics to imaging/analysis software. The role covers RTL architecture, timing closure, interfacing to ADCs/DACs and memory, and verification.

• Architect and implement FPGA/RTL modules (VHDL/Verilog/SystemVerilog) for data capture, digital beamforming primitives, filtering, and high‑speed I/O.
• Define and integrate high‑speed interfaces (LVDS, JESD204B/C, PCIe, DDRx); implement clocking/PLL schemes, resets, and CDC strategies to meet timing.
• Develop verification artifacts (testbenches, simulation, coverage) and support on‑target validation with structured bring‑up procedures.
• Collaborate with hardware and software teams on partitioning, throughput/latency budgets, and DMA/driver integration.
• Create performance tests, profiling tools, and diagnostics; support field/system investigations and root cause analysis.
• Document designs (requirements, micro‑architectures, interface specs) and contribute to risk management and traceability.

• Bachelor’s or Master’s in Electrical/Computer Engineering (or related).
• 5–8+ years in FPGA/SoC development for high‑speed data‑acquisition or signal‑processing systems.
• Proficiency in RTL design, timing closure, and constrained‑random/simulation methodologies; experience with vendor toolflows (Intel/AMD/Xilinx).
• Hands‑on integration with ADC/DACs, external memory, and high‑speed links; strong lab debug skills.
• Solid understanding of DSP fundamentals (sampling, filtering, decimation/interpolation, numerics/fixed‑point).

• Ultrasound or phased‑array experience (beamforming/beamsteering, apodization, delay pipelines).
• C/C++ or Python for tooling/algorithms; Matlab for model‑to‑RTL correlation; familiarity with IEC 62304 documentation expectations.
• Experience with GPU/CUDA or heterogeneous acceleration.

Own core digital pipelines for cutting‑edge ultrasound systems and see your designs translate directly into image quality and performance.

The above information on this job description and specification has been designed to indicate the general nature and level of work performed by employees within this job. It is not designed to contain or be interpreted as a comprehensive inventory of all duties, responsibilities, and qualifications required of employees assigned to this job.